1. Field of the Invention:
The present invention relates to a pulse-width modulation type inverter apparatus for outputting a variable amplitude voltage or variable frequency a.c. voltage, and particularly to an improvement in the control for prevention of a short circuit between controllable elements used as switching elements.
2. Description of the Related Art:
FIG. 16 is a block diagram showing the construction of a conventional pulse-width modulation type inverter apparatus (hereinafer called "PWM type inverter"). In the same drawing, designated at numeral 10 is a d.c. power supply and numeral 20 indicates a power inverter composed of controllable switching elements and diodes connected to each other in antiparallel form, said inverter being adapted to convert a d.c. voltage fed from the d.c. power supply 10 into a variable amplitude or variable frequency a.c. voltage (for the brevity of description, electrical symbols representative of only a single phase are shown here although the inverter is applicable to three-phase voltage generation). Numeral 30 indicates an electric motor which is to be driven by the PWM type inverter. Designated at numeral 40 is a reference voltage generator corresponding to a reference signal generating means for outputting waveforms indicative of reference voltages, i.e., reference-voltage waveforms as references of output frequencies or output voltages. Numeral 50 indicates a carrier generator for generating a carrier waveform of a frequency fc with a triangular waveforms or the like so as to output the same therefrom. Numeral 60 indicates a PWM circuit for generating each striking signal (PWM signal) for each controllable element provided in the power inverter 20 based on signals from the reference voltage generator 40 and the carrier generator 50. Designated at numeral 65 is a processing means for generating each PWM signal by which a short-prevention period T.sub.d is established, based on each signal from the PWM circuit 60 with a view toward preventing a short circuit between upper and lower controllable elements corresponding to each phase designated by the power inverter 20. Numeral 70 indicates a drive circuit for driving each controllable element provided in the power inverter in response to each signal from the processing means 65.
A description will now be made on the operation of the above apparatus. FIG. 18 is a graphic representation of the shapes of waves that typically indicate a PWM operation of this type of PWM type inverter, e.g., FIG. 18 illustrates waveforms for describing the operation of a single U phase employed in the PWM type inverter, out of three phases of U, V and W. As shown in FIG. 17, the reference voltage as a reference of an output voltage or output frequency of the inverter is compared with a signal for modulating the same, e.g., a signal indicative of a carrier waveform as a triangular wave. As shown in FIG. 18(a), period during which the reference voltage is larger than a voltage of the carrier waveform causes the PWM signal to be brought into an on state, while a period during which the reference voltage is smaller than the carrier waveform voltage causes the PWM signal to be brought into an off state, thereby making it possible to obtain the result, as a PWM signal U.sub.PO for the upper-side controllable switching element corresponding to the U phase. A PWM signal U.sub.NO for the lower-side controllable switching element, which corresponds to the U phase, is generated by inverting the PWM signal U.sub.PO. In order to prevent the upper-side and lower-side controllable elements from being short circuited, each controllable element is actually driven by short-prevention processed PWM signals UP, U.sub.N which delay on-timing by a time interval corresponding to the short-prevention period T.sub.d. As a result, an output voltage corresponding to the U phase is pulse-width modulated in the form of a sine wave, thereby obtaining an output voltage waveform shown in FIG. 18(d). Incidentally, each of output voltages corresponding to V and W phases can be obtained in the above-described manner. A potential shown in FIG. 18(d) represents one corresponding to an imaginary neutral point on a d.c. side.
The above-described reference voltage waveform and carrier waveform are shown in FIG. 18(a). The PWM signals U.sub.PO and U.sub.NO are depicted in FIG. 18(b) and the output voltage is illustrated in FIG. 18(d). Referring to FIG. 16, the reference voltage generator 40 serves to output a reference voltage waveform shown in FIG. 18(a). The carrier generator 50 serves to generate a carrier waveform in the form of a triangular wave depicted in FIG. 18(a) and the PWM circuit 60 serves to generate a PWM signal illustrated in FIG. 18(b). In addition, the processing means 65 serves to generate a short-prevention processed PWM signal depicted in FIG. 18(c) and the drive circuit 70 activates controllable elements provided in the power inverter 20 using a PWM signal subsequent to a short prevention processing by the processing means 65. The PWM inverter can bring about a variable a.c. voltage or variable a.c. frequency in the above-described manner.
Meanwhile, the influence of the short-prevention period T.sub.d on the output voltage will occur as shown in FIGS. 19 and 20. Its influence differs depending on the polarity of the output current. When the polarity of the output current is positive, the output voltage is outputted at a value lower than the reference voltage during the short-prevention period T.sub.d. When the polarity of the output current is negative on the other hand, the output voltage is outputted at a value higher than the reference voltage. Thus, the output voltage is affected by the polarity period of the output current, thereby causing distortion represented by V.sub.UN in FIG. 20 owing to an ideal sine wave obtained by reference PWM signal. In addition, the manner of occurrence of distortion in the output voltage is also shown in FIG. 18(e) as distortion (error) which appears in association with the current polarity. Here, V.sub.U-O, V.sub.UO-O each represent a potential in the case where an imaginary neutral point on the d.c. side is considered as a reference.
In other words, an error will occur in a reference voltage signal by the short-prevention period T.sub.d This error is undesirable because of the distortion of the output voltage, the reduction in the output voltage and an increase in torque ripples.
A description will next be made of the PWM type inverter which has been proposed for the purpose of solution of such inconvenience.
FIG. 21 is a block diagram showing the construction of the conventional PWM type inverter which has been disclosed in Japanese Patent Laid-Open No. 60-207494. Designated at numeral 55 is a potential detector for detecting the level of each logic output voltage corresponding to each phase. Numeral 60a indicates a PWM circuit as a PWM signal generating means for generating each striking signal (PWM signal) for each controllable element provided in a power inverter 20, based on signals from a reference voltage generator 40 and a carrier generator 50 and a signal from the potential detector 55. The same elements of structure as those shown in FIG. 16 are identified by like reference numerals and its description will therefore be omitted. A description will hereinafter be made of the operation of correction of the influence of the short-prevention period T.sub.d on the output voltage. In the conventional example shown in FIG. 21, the potential detector 55 for detecting the level of the logic output voltage corresponding to each phase is provided in order to solve the above-described inconvenience. Then, the output signal from the potential detector 55 is compared with the reference PWM signal [e.g., U.sub.PO U.sub.NO shown in FIG. 18(b)] prior to the short-prevention processing, so that the difference between the voltages corresponding to the signals referred to above is corrected successively.
FIG. 22 is a circuit diagram showing the potential detector 55 in detail, and shows an output unit of the PWM type inverter, corresponding to the U phase. A resistor 15 and a photocoupler 16 are interposed between a U phase output terminal and a d.c. bus N. When the signal Up is positive, the U phase terminal is connected to a d.c. bus P, i.e., the potential is brought into P level, the photocoupler 16 is made conductive, and a detection signal PC, is brought into H level. On the other hand, when the signal UN is positive the U phase output terminal is connected to the d.c. bus N, the photocoupler 16 is made nonconductive, and the deletion signal PC is brought into L level. In the above-described manner, the logic level (polarity) of the actual output voltage is detected, thereby to output the result of detection to the PWM circuit 60a. Incidentally, the operations of V and W phases are also the same as that in the above-described embodiment and their description will therefore be omitted.
A description will next be made of the operation of the potential detector in combination with FIG. 23. For example, a reference signal representative of U.sub.PO is compared with a detection signal PC indicative of a potential corresponding to the U phase from the potential detector 55 and errors corresponding to time delays of the change timing from, e.g., L level to H level are accumulated by a counter or the like. When a time delay is made by the time corresponding to the above-accumulated errors during a period of the next change timing from H level to L level and a command is given by the reference signal U.sub.PO, the time interval indicative of H level is secured only during the same period (the time interval indicative of L level is also secured similarly to the time interval indicative of H level), whereby the error correction is performed so as to obtain a given output voltage As shown in FIG. 23, the graphic representation of the shapes of waves that indicate the operational characteristics about the error correction includes only a short prevention period T.sub.d and a time delay T.sub.s representative of an off state of a main circuit element, and other delay elements are not included therein. In the drawing, UDLY corresponds to a PWM signal subsequent to the correction of the signal U.sub.PO and PC corresponds to a signal obtained by detecting the result of operation of elements by the short-prevention processed PWM signal U.sub.p from the signal UDLY. In addition .SIGMA.U represents the result of integration or counting of errors in signal between the reference signal and the detection signal.
This proposed apparatus, it is practiced to correct, for example, a time delay indicative of the change timing from L level to H level, which has been stored as data about the time interval between t.sub.2 and t.sub.1 , by delaying the next change timing from H level to L level by a time of transition from t.sub.3 to t.sub.4.
6a and 6b represent the state of striking of arc (H level) and extinction of arc (L level) of the upper- and lower-side controllable elements corresponding to the U phase, which are shown in FIG. 22, respectively.
As an alternative to the above-described method, there has been proposed a PWM type inverter for controlling the influence of the short-prevention period T.sub.d on the output voltage.
FIG. 24 is a block diagram showing the construction of another conventional PWM type inverter. Numeral 90 is a current detector for detecting output current from the inverter. Numeral 100 indicates a polarity discriminating means which is responsive to an output signal from the current detector 90 for judging whether or not the polarity of output current corresponding to each phase of the inverter is positive or negative. Designated at numeral 40c is a reference voltage generator which is responsive to an output signal from the polarity discriminating means 100 so as to output each reference voltage waveform for correcting each waveform of signals corresponding to preestimated errors such that the output voltage from the inverter becomes the reference voltage. Numeral 60 indicates a PWM circuit for generating each striking signal (PWM signal) for each controllable element provided in a power inverter 20, based on output signals from the reference voltage generator 40c and a carrier generator 50.
The same elements of structure as those shown in FIG. 21 are identified by like reference numerals in FIG. 24 and their description will therefore be omitted.
A description will next be made of the operation of the inverter referred to above. In this PWM type inverter, as shown in FIG. 24, the current detector 90 and the polarity discriminating means 100 are provided in place of the potential detector 55. It is practiced in this unit to judge whether or not the polarity of output current corresponding to each phase is positive or negative and correct each reference voltage waveform according to the polarity of the output current in the direction in which output current affected by the short-prevention period T.sub.d is cancelled.
FIG. 25 illustrates waveforms for describing the operation for the correction of each reference voltage waveform according to the polarity of the output current. FIG. 25 depicts each waveform for describing the operation of correction of the reference voltage waveform corresponding to a U phase alone out of three phases, in an illustrative example representing the case where three-arm control of a type wherein the three phases are always subjected to switching during each cycle period of each of the carrier waveforms shown in FIGS. 18, 19 and 20, is performed.
FIG 25(a ) shows a reference voltage waveform and FIG. 25(b) depicts an output current waveform. FIG. 25(c) is a waveform obtained by replacing the level of a voltage .DELTA.V corresponding to distortion of an output voltage waveform affected by the short-prevention period T.sub.d by the level of the reference voltage waveform. FIG. 25(d) is a waveform representing a polarity discriminating signal S.sub.2 as output current and FIG. 25(e) is a waveform representing the level of a voltage for correcting the reference voltage waveform in the direction in which the level of the voltage .DELTA.V corresponding to the distortion of the output voltage waveform is present. In addition, FIG. 25(f) depicts a phase voltage waveform corresponding to the U phase, having distortion components caused by the influence of the short-prevention period T.sub.d on the output voltage and indicated by the solid line, with respect to a target voltage indicated by the broken line (in practice, FIG. 25(f) shows a PWM waveform, which is in turn represented by analog values for the brevity of description).
As has been described in the article entitled "Short-Prevention Period Regarding Upper and Lower Arms Employed In PWM Inverter" published at the meeting of the Association of Tokai Branch sponsored by the Institute of Electrical Engineering, in 1982 (Showa 57 nendo Denki Gakkai Tokaishibu Rengotaikai), the voltage .DELTA.V corresponding to the distortion of the output voltage waveform is established by the following expression: EQU .DELTA.V .varies.f.sub.c .multidot.T.sub.d
where
f.sub.c =carrier frequency
T.sub.d =short-prevention period
Let's now assume that such output current I.sub.U as shown in FIG. 25(b) flows in a state in which an electric motor 30 has been driven by the inverter. At this time, the current detector 90 serves to detect the above-described output current I.sub.U, and the polarity discriminating means 100 supplies a polarity discriminating signal S2 shown in FIG. 25(d) to the reference voltage generator 40c based on the signal detected by the current detector 90. Then, the reference voltage generator 40c is responsive to the polarity discriminating signal S2 for generating a correction signal in the direction in which the influence of the short-prevention period T.sub.d on the output voltage, i.e., the voltage .DELTA.V corresponding to the distortion of the output voltage waveform shown in FIG. 25(c) is cancelled, and for adding the generated signal to the reference voltage waveform depicted in FIG. 25(a) so as to supply the result of addition to the PWM circuit 60. In the above-described manner, the reference voltage waveform is corrected and PWM-calculated in such a way that the influence of the short-prevention period T.sub.d is cancelled in advance according to the polarity of the output current for obtaining an output voltage. Thus, such distortion as indicated by the solid line in FIG. 25(f) is controlled, thereby obtaining such an output voltage waveform as indicated by the broken line.
The conventional pulse-width modulation type inverter apparatus is constructed as described above. Where the short-prevention period T.sub.d is established by the processing means 65 so as to avoid a short circuit between the controllable elements, the short-prevention period T.sub.d exerts a negative influence upon the output voltage. In addition, where the potential detector 55 detects a voltage at each of the junction points between the controllable elements of the inverter arms and the influence of the short-prevention period T.sub.d on the output voltage is corrected by the PWM circuit 60 based on the detected voltage, the logic level of the output voltage to be generated by the potential detector 55 is not established in a region in which the output current is rendered minimum. It is thus impossible to correct the influence of the short-prevention period T.sub.d by the logic correction. Furthermore, where a judgement is made by the polarity discriminating means 100 as to whether or not the polarity of the output current detected by the current detector 90 is positive or negative and a correction signal corresponding to the discriminating signal S2 is generated by the reference signal generator 40c, and the voltage corresponding to the correction signal is added to the reference voltage, thereby correcting the influence of the short-prevention period T.sub.d on the output voltage, a limitation is imposed on the accuracy in discrimination of the polarity discriminating means 100 in zero level region of output current, in which the polarity of the output current is changed from positive to negative or vice versa, thereby causing difficulty in discrimination of the polarity with high accuracy. The influence of the short-prevention period T.sub.d on the output voltage appears remarkably in the vicinity of changeover in the polarity of the output current and hence the period during which the output current remains in the vicinity of the zero level is rendered long. As a result, a period representative of the result of the polarity discrimination of positive or negative is rendered unbalanced in correlation with the limitation of accuracy in the polarity discrimination. In addition, detection errors occur in each point at which the above polarity is to be changed, and hence the influence of the short-prevention period T.sub.d on the output voltage cannot be corrected, thereby causing a problem to be solved by the invention, that the distortion in the output voltage, the reduction in the output voltage, the torque ripples, the irregularity in rotation, etc. is produced.